9-5 9 1 8 top view 2 3 4 5 6 7 16 9 15 14 13 12 11 10 AP0332 8 p-channel latchable power mosfet array ordering information general description the supertex AP0332 is an 8 p-channel 320v common source power mosfet array with a cmos 8 bit addressable latch. the outputs are guaranteed to have very low leakage current. the outputs are addressed by logic inputs a0, a1, and a2. the addressed and unaddressed output can be turned on or off by the data, set, and write disable inputs. the AP0332 is ideally suited for low leakage/high impedance measurements, providing excellent accuracy as well as resolution for automatic bare board test equipment and other applications. features low drain to source leakage interfaces directly to ttl and cmos logic 8 independent channels low crosstalk between channels low power dissipation freedom from secondary breakdown serial data input on-chip decoder, latch with set and write disable circuitry absolute maximum ratings 1 off-state output voltage, v oo -320v logic supply voltage, v dd -0.5v to +15v logic input levels, all inputs -0.5v to v dd operating and storage temperature range -55 c to +150 c soldering temperature 2 300 c channel-to-channel crosstalk 10mv/v notes: 1. all voltages are referenced to v ss . 2. distance of 1.6mm from case for 10 seconds. applications high impedance/low leakage measurements for bare board testers high voltage piezoelectric transducer drivers high voltage electroluminescent panel drivers high voltage electrostatic array drivers general multi-channel driver arrays pin configuration q 7 v dd set q 6 data q 5 w rite dis q 4 a 0 q 3 a 1 q 2 a 2 q 1 v ss q 0 note: see package outline section for dimensions. so-16 v dd r o(on) i o(on) i o(off) order number/package (max) (max) (min) (max) so-16 die -320v 700 ? -15ma -1.0na AP0332cg AP0332nd *average current per channel, measured with all eight channels connected in parallel. C obsolete C
9-6 symbol parameter min typ max unit conditions i o(off) off-state output current -8.0 na v o = max. rating, 8 outputs connected in parallel i o(on) on-state output current -15 ma v o = 25v r o(on) on-state output resistance 700 ? i o = -10ma ? r o(on) change in r o(on) with high temperature 0.8 %/ ci o = -10ma i ddq quiescent logic supply current 0.05 16.5 a v il input low voltage 3.5 v v ih input high voltage 12 v i in input current 1.0 a note: 1. all voltages are referenced to v ss . electrical characteristics (@ 25 c and v dd = 12v unless otherwise specified) dc characteristics symbol parameter min typ max unit fig. 1* conditions t d(on) turn-on delay time 800 ns 1a t d(off) turn-off delay time 800 ns 1b t r rise time 200 ns 10 t f fall time 200 ns 11 t phl , t plh propagation delay time 87 ns 2 v o = 25v, i o = -10ma from write disable to output t phl , t plh propagation delay time 87 ns 3 from set to output t phl , t plh propagation delay time 107 ns 9 from address to output t w minimum pulse width ?data 50 100 ns 4 t w minimum pulse width ?address 100 200 ns 8 t w minimum pulse width ?set 40 75 ns 5 t s setup time ?data to write disable 50 ns 6 t h hold time ?data to write disable 75 ns 7 c in input capacitance ?any input 5.0 7.5 pf *refer to circled numbers on timing diagram (figure 1). note: 1. all voltages are referenced to v ss . ac characteristics AP0332 C obsolete C
9-7 9 symbol parameter v dd min max unit v dd logic supply voltage 10.0 13.2 v v o output voltage referenced to v dd 0 -320 v v ih input high voltage 12v v dd - 2 v dd v v il input low voltage 12v 0 2.0 v t a operating free-air temperature 0 70 c note: 1. all voltages are referenced to v ss . a 0 , a 1 , a 2 5 6 7 8 9 1a 11 10 1b 2 3 4 write disable data set t w t p t p t r t w t p t f t d(on) t d ( off ) t h t s t w q 0 on q 0 off q 7 on q 7 off recommended operating conditions (for maximum reliability, nominal operating conditons should be selected so that operation is always within the following range s.) AP0332 data write disable set addressed output unaddressed outputs hl l off holdspriv. l on hh l holdspriv. holdspriv. l hlh off off l on hhhoff off l mode selection t iming diagram figure 1 C obsolete C
9-8 q 7 v dd (+) s set v ss (? q 6 q 5 q 4 a 1 a 0 a 2 q 3 q 2 q 1 q 0 latch latch latch latch latch latch latch latch 3:8 decoder w rite disable data functional block diagram AP0332 C obsolete C
|
